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Reduction of Bitstream Size for Low-Cost iCE40 FPGAs

EasyChair Preprint no. 8661

6 pagesDate: August 11, 2022


Reducing the bitstream size is important to lower external storage requirements and to speed-up the reconfiguration of field-programmable gate arrays (FPGAs). The most common methods for bitstream size reduction are based on dedicated hardware elements or dynamic partial reconfiguration. All of these properties are usually missing in low-cost FPGAs such as the Lattice iCE40 device family.

In this paper we propose a lightweight compaction approach for iCE40 FPGAs. We present five methods for bitstream compaction: two adapted and three new. The methods work directly on the bitstream by removing unnecessary data and redundant commands. They are applicable independent of the synthesis toolchain and require neither repetition of synthesis steps nor modifications of the target system. Although our focus is on iCE40 devices, we also discuss the conditions for applying our approach to other targets.

All five methods were implemented in an open-source compaction tool. We evaluate our approach with an iCE40 HX8K FPGA by synthesizing and compacting various projects. As a result, we achieve a reduction in bitstream size and reconfiguration time by up to 79 %.

Keyphrases: bitstream, Compaction, Compression, FPGA, iCE40

BibTeX entry
BibTeX does not have the right entry for preprints. This is a hack for producing the correct reference:
  author = {Clemens Fritzsch and Joern Hoffmann and Martin Bogdan},
  title = {Reduction of Bitstream Size for Low-Cost iCE40 FPGAs},
  howpublished = {EasyChair Preprint no. 8661},

  year = {EasyChair, 2022}}
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